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ga100jt12 - 227 dec 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 1 of 11 normally ? off silicon carbide junction transistor features package ? 175 c maximum operating t emperature ? gate oxide free sic s witch ? optional gate return pin ? exceptional safe operating area ? excellent gain linearity ? temperature independent s witchi ng p erformance ? low output capacitance ? positive temperature coefficient of r ds, on ? suitable for connecting an anti - parallel d iode isolated baseplate sot -227 advantages applications ? compatible with si mosfet/igbt gate drive ics ? > 20 s short - circuit withstand capability ? lowest - in - class conduction losses ? high circuit efficiency ? minimal input signal distortion ? high amplifier bandwidth ? reduced cooling requirements ? reduced system size ? down hole oil drilling, geothermal instrumentation ? hybrid electric vehicles (hev) ? solar inverters ? switched - mode power supply (smps) ? power factor correction (pfc) ? induction heating ? uninterruptible power supply (ups) ? motor drives table of contents section i: absolute maximum ratings ................................ ................................ ................................ .......... 1 section ii: static electrical characteristics ................................ ................................ ................................ ... 2 section iii: dynamic electrical characteristics ................................ ................................ ............................ 2 section iv: figures ................................ ................................ ................................ ................................ .......... 3 section v: driving the ga100jt12 - 227 ................................ ................................ ................................ ......... 7 section vi: package dimensions ................................ ................................ ................................ ................. 11 section vii: spice model parameters ................................ ................................ ................................ ......... 1 2 section i: absolute maximum ratings parameter symbol conditions value unit notes drain ? source voltage v ds v gs = 0 v 12 00 v continuous drain current i d t c = 2 5c 160 a fig. 16 continuous drain current i d t c = 11 5c 10 0 a fig. 16 continuous gate current i g 7 a continuous gate return current i gr 7 a turn - off safe operating area rbsoa t vj = 175 o c, clamped inductive load i d,max = 100 @ v ds v dsmax a fig. 18 short circuit safe operating area scsoa t vj = 175 o c, i g = 1 a , v ds = 8 00 v, non repetitive >20 s reverse gate ? source voltage v sg 30 v reverse drain ? source voltage v sd 25 v power dissipation p tot t c = 25 c / 11 5 c, t p > 100 ms 535 / 214 w fig. 15 operating and storage temperature t stg - 55 to 175 c g s gr d d s g gr v ds = 12 00 v r ds(on) = 1 0 m i d ( tc = 25 c) = 160 a i d (tc = 11 5c ) = 1 0 0 a h fe ( tc = 25c ) = 100 please note: the source and gate return pins are not exchangeable. their exchange might lead to malfunction. pin d - d rain pin s - source pin gr - gate return pin g - g ate
ga100jt12 - 227 dec 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 2 of 11 section ii: static electrical characteristics a: on state b: off state c: thermal section iii: dynamic electrical characteristics a: capacitance and gate charge b: sjt switchi ng characteristics 1 1 ? all times are relative to the drain - source voltage v ds parameter symbol conditions value unit notes min. typical max. drain ? source on r esistance r ds(on) i d = 10 0 a, t j = 25 c i d = 10 0 a, t j = 1 5 0 c i d = 10 0 a, t j = 175 c 1 0 18 21 m fig. 5 gate ? source saturation voltage v gs,sat i d = 10 0 a, i d /i g = 40 , t j = 25 c i d = 10 0 a, i d /i g = 30 , t j = 175 c 3.42 3. 2 3 v fig. 7 dc current gain h fe v ds = 8 v, i d = 10 0 a , t j = 25 c v ds = 8 v, i d = 10 0 a , t j = 12 5 c v ds = 8 v, i d = 10 0 a , t j = 17 5 c 100 65 58 105 ? fig. 4 drain leakage current i dss v ds = 12 00 v, v gs = 0 v, t j = 25 c v ds = 12 00 v, v gs = 0 v, t j = 1 50 c v ds = 12 00 v, v gs = 0 v, t j = 17 5 c 5 0 100 10 0 a fig. 8 gate leakage current i s g v sg = 2 0 v, t j = 25 c 4 0 na thermal resistance, junction - case r thjc 0.28 c/w fig. 20 parameter symbol conditions value unit notes min. typical max. input capacitance c is s v gs = 0 v, v d s = 8 00 v, f = 1 mhz 14. 3 n f fig. 9 reverse transfer/output capacitance c rss /c oss v d s = 8 00 v, f = 1 mhz 2 50 pf fig. 9 output capacitance stored energy e oss v gs = 0 v, v d s = 8 00 v, f = 1 mhz 9 5 j fig. 10 effective output capacitance, time related c os s ,tr i d = constant, v gs = 0 v, v ds = 0?800 v 440 pf effective output capacitance, energy related c os s ,er v gs = 0 v, v ds = 0?800 v 300 pf gate - source charge q gs v gs = - 5?3 v 12 0 nc gate - drain charge q gd v gs = 0 v, v ds = 0?800 v 350 nc gate charge - total q g 4 7 0 nc internal gate resistance ? on r g(int - on) v gs > 2 . 5 v , v ds = 0 v, t j = 17 5 oc 0.1 turn o n delay time t d(o n ) t j = 25 oc, v ds = 8 00 v, i d = 10 0 a, resistive load refer to section v for additional driving information. 12 ns fall time , v ds t f 40 ns fig. 11 , 13 turn o ff delay time t d(o ff ) 37 ns rise time , v ds t r 25 ns fig. 12 , 14 turn o n delay time t d(o n ) t j = 17 5 oc, v ds = 8 00 v, i d = 10 0 a, resistive load 1 0 ns fall time , v ds t f 4 0 ns fig. 11 turn o ff delay time t d(o ff ) 45 ns rise time , v ds t r 20 ns fig. 12 turn - on energy per pulse e on t j = 25 oc, v ds = 8 00 v, i d = 10 0 a, inductive load refer to section v . 1.8 m j fig. 11 , 13 turn - off energy per pulse e off 1.4 m j fig. 12 , 14 total switching energy e t ot 3.2 m j turn - on energy per pulse e on t j = 17 5 oc, v ds = 8 00 v, i d = 10 0 a, inductive load 1.85 m j fig. 11 turn - off energy per pulse e off 1.3 m j fig. 12 total switching energy e t ot 3.15 m j
ga100jt12 - 227 dec 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 3 of 11 section iv: figures a: static characteristic s figure 1: typical output characteristics at 25 c figure 2 : typi cal output characteristics at 1 50 c figure 3 : typical output characteristics at 175 c figure 4: dc current gain vs. drain current figure 5: on - resistance vs. gate current fig ure 6: normalized on- resistance vs. temperature
ga100jt12 - 227 dec 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 4 of 11 figure 7: typical gate ? source saturation voltage figure 8: typical blocking characteristics b: dynamic characteristic s figure 9: input, output, and reverse transfer capacitance figure 10: energy stored in output capacitance figure 11 : typical switching times and turn on energy losses vs. temperature figure 12 : typical switching times and turn o ff energy losses vs. temperature
ga100jt12 - 227 dec 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 5 of 11 figure 13 : typical switching times and turn on energy losses vs. drain current figure 14 : typical switching times and turn o ff energy losses vs. drain current c: current and power derating figure 15 : typical hard switched device power loss vs. switching frequency 2 figure 16: power derating curve figure 17: drain current derating vs. temperature figure 18: forward bias safe operating area at t c = 25 o c 2 ? representative values based on device conduction and switching loss. actual losses will depend on gate drive conditions, device load, and circuit topology
ga100jt12 - 227 dec 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 6 of 11 figure 19: turn - off safe operating area figure 20: tran sient thermal impedance figure 21: drain current derating vs. pulse width
ga100jt12 - 227 dec 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 7 of 11 section v: driving the ga100jt12 -227 drive topology gate drive power consumption switching frequency application emphasis availability ttl logic high low wide temperature range coming soon constant current medium medium wide temperature range coming soon high speed ? boost capacitor medium high fast switching production high speed ? boost inductor low high ultra fast switching coming soon proportional lowest high wide drain current range coming soon pulsed power medium n/a pulse power coming soon a: static ttl logic driving the ga100jt12 - 227 may be driven with direct (5 v) ttl logic and current amplification. the amplified current level of the supply must meet or exceed the steady state gate current (i g,steady ) required to operate the ga100jt12 - 227 . minimum i g,steady is dependent on the antic ipated drain current i d through the sjt and the dc current gain h fe , it may be calculated from the following equation. an accurate value of the h fe may be read from figure 5 . an optional resistor r g may be used in series with the gate pin to trim i g,steady , also an optional capacitor c g may be added in parallel with r g to facilitate faster sjt switching if desired, further details on these options are gi ven in the following section. ? ? , ?????? ? ? ? ?? ( ? , ? ? ) ? 1 . 5 figure 22 : ttl gate drive schematic b: high speed driving the sjt is a current controlled transistor which requires a positive gate current for turn - on and to remain in on - state. an idealized gate current waveform for ultra - fast switching of the sjt while maintaining low gate drive losses is shown in figure 23 , it features a positive current peak during turn - on, a negative current peak during turn - off, and continuous gate current during on - state. figure 23 : an idealized gate current waveform for fast switching of an sjt. an sjt is rapidly switched from its blocking state to on - state when the necessary gate charge, q g , for turn - on is supplied by a burst of high gate current, i g,on , unt il the sjt gate- source capacitance, c gs , and gate - drain capacitance, c gd , are fully charged. ? ?? = ? ? , ?? ? ? 1 ? ?? ? ?? + ? ?? ttl gate signal 5 / 0 v ttl i/p 5 v d s g gr c g r g i g,steady
ga100jt12 - 227 dec 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 8 of 11 ideally, i g,on should terminate when the drain voltage falls to its on - state value in order to avoid unnecessary drive lo sses during the steady on - state. in practice, the rise time of the i g,on pulse is affected by the parasitic inductances, l par in the device package and drive circuit. a voltage developed across the parasitic inductance in the source path, l s , can de - bias the gate - source junction, when high drain currents begin to flow through the device. the voltage applied to the gate pin should be maintained high enough, above the v gs ,sat ( see figure 7 ) level to counter these effects. a high negative peak current, - i g,off is recommended at the start of the turn - off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn - off. turn off can be achieved with v gs = 0 v, however a negative gate voltage v gs may be used in order to speed up the turn - off transition. gate return pin the optional gate return (gr) pin allows for a reduction of source path inductive and r esistive coupling in the gate driver connection to the ga100 jt 12 - 227. drain currents through the source pin during transient and steady state operation induce an undesirable source voltage i n all power transistors due to unavoidable source pin inductance a nd resistance. this voltage can negatively affect gate driving performance, however the gate return pin allows for decoupling from these source current path effects which results in faster switching an d higher efficiency gate driving. b:1: high speed, low loss drive with boost capacitor, ga15iddjt22 - fr4 the ga100jt12 - 227 may be driven using a high speed, low loss drive with boost capacitor topology in which multiple voltage levels, a gate resistor, and a gate capacitor are used to provide fast switching current peaks at turn - on and turn - off and a continuous ga te current while in on - state. an evaluation gate drive board ( ga15iddjt22 - fr4 ) utilizing this topology is commercially ava ilable for high and low - side driving, its datasheet provides additional details. figure 24 : topology of the ga15iddjt22- fr4 two voltage source gate driver. the ga15iddjt22 - fr4 evaluation board comes equipped with two on board gate drive resistors (rg1, rg2) pre - installed for an effective gate resistance 3 of r g = 0.7 ?. it may be necessary for the user to reduce rg1 and /or rg2 under high drain current conditions for safe operation of the ga100jt12 - 227 . the steady state current s upplied to the gate pin of the ga100jt12 - 227 with on - board r g = 0.7 ?, is shown in figure 25 . the maximum allowable safe value of r g for the user?s required drain current can be read from figure 26 . for the ga100jt12 - 227 , r g must be reduced for i d ~ 40 a for safe operation with th e ga15iddjt22 - fr4 . for operation at i d ~ 40 a, r g may be calculated from the following equation, which contains the dc current gain h fe and the gate - source saturation voltage v gs,sat ( figure 7 ). ? ? , ??? = ? 4 . 7 ? ? ? ?? , ??? ? ? ? ?? ( ? , ? ? ) ? ? ? 1 . 5 ? 0 . 1 i g gate source d s g gr cg2 v gh d1 r5 r1 u4 v gl v ee v gl x2 v gh x1 v ee c2 c1 v ee u2 v gl v ee cg1 rg1 rg2 r2 c5 c21 c8 c9 c6 c7 +12 v +12 v vcc high vcc high rtn vcc low vcc low rtn signal signal rtn r3 r4 u1 u3 c4 v gl v ee c10 r6 ga15iddjt22-fr4 gate driver board
ga100jt12 - 227 dec 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 9 of 11 figure 25 : typical steady state gate current supplied by the ga15iddjt22 - fr4 board for the ga100jt12 - 227 with the on board resistance of 0.7 ? figure 26 : maximum gate resistance for safe operation of the ga100jt12 - 227 at different drain currents using the ga15iddjt22 - fr4 board. b:2: high speed, low loss drive with boost inductor a high speed, low - loss driver with boost inductor is also capable of driving the ga100jt12 - 227 at high - speed. it utilizes a gate drive inductor instead of a capacitor to provide the high - current gate current pulses i g,on and i g,off . during operation, inductor l is charged to a specified i g,on current value then made to discharge i l into the sjt gate pin using logic control of s 1 , s 2 , s 3 , and s 4 , as shown in figure 27 . after turn on, while the device remains on the necessary steady state gate current i g,steady is supplied from source v cc through r g . please refer to the article ?a current - source concept for fast and efficient driving of silicon carbide transistors by dr. jacek r?bkowski for additional information on this driving topology. 4 figure 27 : simplified inductive pulsed drive topology 3 ? r g = (1/ rg1 +1/rg2) -1 . driver is pre - installed with rg1 = 2.2 ? , rg2 = 1.0 ? 4 ? archives of electrical engineering. volume 62, issue 2, pages 333 ? 343, issn (print) 0004 - 0746, doi: 10.2478/aee - 2013 - 0026 , june 2013 l r g v ee v cc v cc v ee s 1 s 2 s 3 s 4 d s g gr
ga100jt12 - 227 dec 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 10 of 11 c: proporti onal gate current driving for applications in which the ga100jt12 - 227 will operate over a wide range of drain current conditions, it may be beneficial to drive the device using a proportional gate drive topology to optimize gate drive power consumption. a proportional gate driver relies on instantaneous drain current i d feedback to vary the steady state gate current i g,steady supplied to the ga100jt12 - 227 c:1: voltage controlled proportional driver the voltage controlled proportional driver relies on a gate dri ve ic to detect the ga100jt12 - 227 drain - source voltage v ds during on - state to sense i d . the gate drive ic will then increase or decrease i g,steady in response to i d . this allows i g,steady , and thus the gate drive power consumption, to be reduced while i d i s relatively low or for i g,steady to increase when is i d higher. a high voltage diode connected between the drain and sense protects the ic from high - voltage when the driver and ga100jt12 - 227 are in off - state. a simplified version of this topology is shown in figure 28 , additional information will be available in the future at http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ figure 28 : simplified voltage controlled proportional driver c:2: current controlled proportion al driver the current controlled proportional driver relies on a low - loss transformer in the drain or source path to provide feedback i d of the ga100jt12- 227 during on - state to supply i g,steady into the device gate. i g,steady will then increase or decrease in response to i d at a fixed forced current gain which is set be the turns ratio of the transformer, h force = i d / i g = n 2 / n 1 . ga100jt12 - 227 is initially turned - on using a gate current pulse supplied into an rc drive circuit to allow i d current to begin flowing. this topology allows i g,steady , and thus the gate drive power consumption, to be reduced while i d is relatively low or for i g,steady to increase when is i d higher. a simplified version of this topology is shown in figure 29, additional information will be available in the future at ht tp://www.genesicsemi.com/commercial - sic/sic - junction - transistors/. figure 29 : simplified current controlled pr oportional driver proportional gate current driver gate signal i g,steady hv diode sense signal output d s g gr n 2 n 2 n 1 n 3 gate signal d s g gr
ga100jt12 - 227 dec 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 11 of 11 section vi: package dimensions s o t - 2 2 7 package outline note 1. controlled dimension is inch. dimension in bracket is millimeter. 2. dimensions do not include end flash, mold flash, material protrusions revision history date revision comments supersedes 2015/12/07 2 updated electrical characteristics 2015/09/16 1 updated electrical characteristics 2015/05/29 0 initial release published by genesic semiconductor, inc. 43670 trade center place suite 155 dulles, va 20166 genesic semiconductor, inc. reserves right to make changes to the product specifications and data in this document without notice . genesic disclaims all and any warranty and liability arising out of use or application of any product. no license, express or implied to any intellectual propert y rights is granted by this document. unless otherwise expressly indicated, genesic products are not designed, tested or authorized for use in life - saving, medical, aircraft n avigation, communication, air traffic control and weapons systems, nor in applic ations where their failure may result in death, personal injury and/or property damage. 1.240 (31 .5) 1.255 (31.88) 0.310 (7 .87) 0.322 (8 .18) r 3.97 0.163 (4.14) 0.169 (4 .29) ? 0.163 (4.14) 0.169 ( 4.29) 0.186 (4 .72) 0.191 (4 .85) 0.165 (4.19) 0.169 (4 .29) 0.588 (14 .9) 0.594 (15.09) 1.186 (30.1) 1.192 (30.28 ) 1.494 (37.9) 1.504 (38.20) 0.108 (2 .74) 0.124 (3 .15) 0.372 (9 .45) 0.378 (9 .60) 0.472 (11 .9) 0.480 (12 .19) 0.030 (0.76 ) 0.033 (0.84) 0.495 (12 .5) 0.506 (12.85) 0.990 (25.1 ) 1.000 (25 .40) 1.049 (26.6 ) 1.059 (26 .90) 0.080 (2.03) 0.084 (2 .13) 0.164 (4.16) 0.174 (4. 42) m4 0.172 (4 .37) 0.234 (5 .94)
ga100jt12 - 227 dec 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 1 of 1 section vii: spice model parameters this is a secure document. please copy this code from the spice model pdf file on our website ( http://www.genesicsemi.com/images/products_sic/sjt/ga100jt12- 227_spice.pdf ) into ltspice (version 4) software for simulation of the ga100jt12 -227. * model of genesic semiconductor inc. * $revision: 2 .0 $ * $date: 0 7 - dec- 2015 $ * * genesic semiconductor inc. * 43670 trade center place ste. 155 * dulles, va 20166 * * copyright (c) 2015 genesic semiconductor inc. * all rights reserved * * these models are provided "as is, where is, and with no warranty * of any kind either expressed or implied, including but not limited * to any implied warranties of merchantability and fitness for a * particular purpose." * models accurate up to 2 times rated drain current. * * * start of ga100jt12- 227 spice model * .subckt ga100jt12 drain gate source q a drain gate source ga100jt12_q q b drain gate source ga100jt12_q * .model ga100jt12_q npn + is 9.833e- 48 ise 1.073e- 26 eg 3.23 + bf 110 br 0.55 ikf 9000 + nf 1 ne 2 rb 0.95 + re 0.005 rc 0.014 cjc 2.12e - 9 + vjc 3.788 mjc 0.537 cje 6.026e- 09 + vje 3.1791 mje 0.5295 xti 3 + xtb - 1.5 trc1 9.0e- 03 mfg genesic_semi + irb 0.005 rbm 0.073 .ends * * end of ga100jt12- 227 spice model

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